Digital signal processors (DSP), designed for a range of applications and having a variety of architectures, commonly employ a number of peripheral device functions. FIG. 1 illustrates a conventional DSP architecture. DSP core 101 communicates to memory 102 using bus 100. Bus 100 is a complex bus that includes program read, data read and data write busses. A separate peripheral bus M bus 112 allows for data transfers among on-chip memory 102, multi-channel buffered serial ports (MCBSP) 107 and host port interface (HPI) 115. Direct memory access (DMA) controller 105 manages these data transfers. Multi-channel buffered serial ports 107 also have a direct communication link with DSP core 101 via bus 110 and with memory 102 via M bus 112. Configuration bus 103 enables DSP core 101 access to configure peripherals such as general purpose timers 104, watchdog timer (WDT) 106, general purpose I/O 108, DMA controller 105, and most importantly for this invention, multi-channel buffered serial ports 107.
FIG. 2 illustrates the construction of multi-channel buffered serial ports (McBSP) 107. McBSP 107 consists of a data path and a control path connected to external devices by seven pins. The external interface signal pins are listed in Table 1. Note: type I is an input; type O is an output; and type Hi-Z has a high impedance when not in use.
TABLE 1PinTypeDescriptionCLKRI/O/Hi-ZReceive ClockCLLXI/O/Hi-ZTransmit ClockCLKSIExternal ClockDRIReceived Serial DataDXO/Hi-ZTransmitted Serial DataFSRI/O/Hi-ZReceive Frame SynchronizationFSXI/O/Hi-ZTransmit Frame Synchronization
McBSP 107 communicates with interfacing devices via data transmit (DX) pin 210 for transmit operations and data receive (DR) pin 211 for receive operations. Control information in the form of clocking and frame synchronization is communicated via CLKX 213, CLKR 214, FSX 215 and FSR 216. DSP core 101 communicates with McBSP 107 through 16-bit-wide control registers accessible via the 16-bit or 32-bit internal peripheral bus 232.
DSP core 101 or DMA controller 105 reads the received data from the data receive registers (DRR[1,2]) 224 and writes the data to be transmitted to the data transmit registers (DXR[1,2]) 225. Data written to DXR[1,2] is shifted out to DX pin 210 via the compress block 231 and the transmit shift register XSR[1,2] 227.
Similarly, receive data on DR pin 211 is shifted into the receive shift registers RSR[1,2] 226 and copied into the receive buffer registers RBR[1,2] 228. Data in RBR[1,2] 228 is then passed through expander block 230 and copied into data receive registers DRR[1,2] 224. DDR[1,2] 224 can be read by DSP core 101 or DMA controller 105. The separate datapaths for transmit and receive allow for simultaneous movement of internal and external data communications.
Table 2 lists the datapath registers 224 to 228 just described and the control registers 201 to 208 accessible to DSP core 101 to configure the control mechanism of McBSP 107.
TABLE 2AcronymRegister NameDatapath RegistersRBR[1, 2]Receive Buffer RegistersRSR[1, 2]Receive Shift RegistersXSR[1, 2]Transmit Shift RegistersDRRData Receive RegisterDXRData Transmit RegisterControl RegistersSPCRSerial Port Control RegisterRCRReceive Control RegisterXCRTransmit Control RegisterSRGRSample Rate Generator RegisterMCRMulti-Channel RegisterRCERReceive Channel Enable RegisterXCERTransmit Channel Enable RegisterPCRPin Control Register
Control block 233 consists of internal clock generation, frame synchronization signal generation 238, control block 234, multi-channel selection control logic 236 and channel control logic 237. Control block 233 sends notification of important events to the cognizant subsystem (DSP core 101 and DMA controller 105) via the two interrupt signals 218 and 219. These signals are collectively referred to as bundle 240. Four event signals REVT 220, XEVT 221, REVTA 222 and XEVTA 223 convey synchronization to local DMA controller 105. These signals are collectively referred to as bundle 241. Table 3 describes these signals.
TABLE 3Interrupt NameDescriptionRINTReceive Interrupt to CPUXINTTransmit Interrupt to CPUREVTReceive Synchronization Event to DMAXEVTTransmit Synchronization Event to DMAREVTAReceive Synchronization Event A to DMAXEVTATransmit Synchronization Event A to DMA
The most recent version of McBSP 107 includes the following enhancements to earlier designs. The new version supports up to 512 channels with individual enable/disable control through PDMA. The corresponding maximum serial clock rate equals the maximum clock rate at one-half of the module clock rate in multi-channel operation. The new version supports up to 512 channels with individual μ-Law and A-Law companding control capability. The new version presents time slot identification to DMA controller 105 and DSP core 101 whenever it asserts a request corresponding to either a transmit event or a receive event. The time slot buffering is incorporated into DMA controller 105. The new version supports super frame synchronization.